1. Field of the Invention
This invention relates to the manufacture of semiconductor devices, in particular, dynamic random access memories having self-aligned shallow trench isolation regions for isolating various transistors within a memory array.
2. Description of Related Art
In fabricating integrated circuits (ICs), the IC usually requires that individual active and passive circuit elements be electrically isolated from each other in a common semiconductor chip so that desired circuit connections may be made by patterned surface metallization with which the isolated circuit elements are in contact. Typically, a memory cell in an array of cells isolates the active circuit element from the passive circuit element, and itself must be isolated from adjacent cells and circuit elements. In addition to the memory cell array, many diverse techniques have been proposed over the years to electrically isolate the active and passive circuit elements including lithographic masking levels, junction isolation, dielectric isolation, and combinations thereof.
As the integration density of a Dynamic Random Access Memory (DRAM) steadily increases, including those having vertical trench capacitors, it becomes necessary to reduce the memory cell array size. In the fabrication of DRAMs, the memory cell size, or isolation region, is primarily determined by the minimum resolution dimension of a lithographic masking technique, the overlay tolerances between the different features of the memory cell size, and the layout of such features, while still maintaining the minimum required storage capacitance to reliably operate the DRAM. However, as the conventional integrated circuit DRAM cells are scaled to decreasingly smaller dimensions with advanced generations of memory products, the integration density of the memory array is increased, and as such, in order to meet the cell size and storage capacitance requirements, the associated process technology complexity of the DRAM cells increases, as well as the costs required to produce such modern high density memory arrays.
As IC dimensions get smaller and device densities increase, it becomes more difficult to efficiently and reliably isolate the active and passive circuit elements of the IC, as well as do so at a decreased cost. Prior art is aimed at using lithographic masking levels for isolating the active and passive circuit elements; however, the inclusion of lithographic masking levels in the fabrication of ICs introduces a variety of problems including processing complexities and fabrication errors, which may lead to inefficient and unreliable ICs, in turn leading to increased production costs. Thus, a need exists in the art to reduce the number of lithographic masking levels required for IC processing, thereby reducing the processing costs and complexity of the resultant chip.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method and assembly for eliminating conventional lithographic masking levels used to delineate the isolation region within a memory cell array during IC fabrication by forming a self-aligned shallow trench isolation structure in an IC array, preferably in a DRAM array.
Another object of the present invention is to provide a method and assembly for eliminating a fine feature size lithographic masking level in an array.
It is another object of the present invention to provide a method and assembly for reducing the complexity of the high-density memory product.
A further object of the invention is to provide a method and assembly for reducing fabrication costs in high-density memory products.
It is yet another object of the present invention to provide an efficient and reliable isolation process to isolate the smaller active and passive circuit elements of modern ICs.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.